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2026-08-07linux-user/mips: write the floating-point registers to a core dumpMatt Turner
Write an NT_FPREGSET note for MIPS and MIPS64, matching the kernel's elf_fpregset_t layout (ELF_NFPREG = 33): fpr[0..31] hold f0-f31, and fcsr occupies the low 32 bits of slot 32. The pad field rounds the struct to 33 × 8 bytes = 264 bytes. Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Helge Deller <deller@gmx.de>
2026-05-29linux-user/mips: save/restore FCSR across signal deliveryMatt Turner
QEMU keeps the MIPS FPU control/status register (FCSR, fcr31) in env->active_fpu.fcr31. The rounding mode, flush-to-zero (FS), and NaN-2008 mode bits in fcr31 are reflected into the derived env->active_fpu.fp_status via set_float_rounding_mode() and friends; every architectural write to FCSR goes through helper_ctc1() which calls restore_fp_status() to keep the two in sync. Both target_sigcontext variants (O32 and N32/N64) have an sc_fpc_csr field that holds FCSR, but setup_sigcontext() never wrote it and restore_sigcontext() never read it. As a result: - The signal frame always delivered sc_fpc_csr == 0 to the handler, so sigaction(SA_SIGINFO) handlers that inspect the interrupted context see the wrong FCSR. - On sigreturn, active_fpu.fcr31 retained whatever value the signal handler last installed (if any), and active_fpu.fp_status was never resynced. Interrupted code resumed with the wrong rounding mode, FS flag, and NaN-2008 semantics. Fix setup_sigcontext() to save fcr31 into sc_fpc_csr. Fix restore_sigcontext() to read it back (masked to fcr31_rw_bitmask as the kernel does) and call cpu_mips_restore_fp_status() to resync fp_status from the restored fcr31. Add cpu_mips_restore_fp_status() in target/mips/fpu.c (which already defines ieee_rm and includes fpu_helper.h), and declare it in cpu.h. Fixes: 084d0497a0 ("mips-linux-user: Save and restore fpu and dsp from sigcontext") Cc: qemu-stable@nongnu.org Signed-off-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Helge Deller <deller@gmx.de>
2026-05-24linux-user/mips: use tswap32 in elf_core_copy_regsMatt Turner
Signed-off-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Helge Deller <deller@gmx.de>
2026-05-24linux-user/mips64: fix elf_core_copy_regs register layout in core filesMatt Turner
mips64/elfload.c uses #include "../mips/elfload.c" to share code. When the compiler processes mips/elfload.c the quoted #include "target_elf.h" resolves relative to the including file's directory, so it picks up mips/target_elf.h instead of mips64/target_elf.h. mips/target_elf.h pulls in mips/target_ptrace.h, whose target_pt_regs has a pad0[6] field before regs[]. As a result elf_core_copy_regs writes: r->pt.regs[i] -> reserved[6+i] (shifted by 6 from the correct index) r->pt.cp0_epc -> reserved[40] (correct mips64 N64 index is 34) The Linux kernel and glibc both use the mips64 N64 layout (no pad0): EPC at reserved[34]. Debuggers and libunwind reading the core with N64 constants therefore see a completely wrong register set — EPC points to GP, RA holds the branch target instead of the link address, etc. Fix by: - Guarding the mips32 elf_core_copy_regs in mips/elfload.c with #ifndef TARGET_MIPS64 so it is not compiled for mips64/mipsn32 targets. - Providing a mips64-specific elf_core_copy_regs in mips64/elfload.c that writes directly to r->reserved[i] with the correct N64 indices, bypassing the struct field names that are tainted by the wrong header include. The mipsn32 (TARGET_ABI_MIPSN32) and mips64el targets are covered by the same mips64/elfload.c and benefit from the same fix. Signed-off-by: Matt Turner <mattst88@gmail.com> Cc: qemu-stable@nongnu.org Signed-off-by: Helge Deller <deller@gmx.de>
2026-05-21linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accessesJames Hilliard
Linux/MIPS enables software fixups for user-mode unaligned scalar accesses by default through MIPS_FIXADE/TIF_FIXADE. QEMU linux-user did not model that ABI, so MIPS guests took fatal AdEL/AdES exceptions unless translation was forced to use unaligned host accesses. Key MIPS translation blocks on the linux-user unaligned policy, implement sysmips(MIPS_FIXADE) to toggle that policy, and raise SIGBUS/BUS_ADRALN when fixups are disabled. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-4-philmd@linaro.org>
2026-05-21linux-user/mips: implement sysmips(MIPS_ATOMIC_SET)James Hilliard
Implement the MIPS_ATOMIC_SET sysmips command as an aligned 32-bit atomic exchange in target memory. MIPS reports syscall errors through a separate register, so successful old values can overlap the errno range. Write the return value and error flag directly and return -QEMU_ESIGRETURN so the common syscall path leaves the registers unchanged. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-3-philmd@linaro.org>
2026-05-21linux-user/mips: implement sysmips(MIPS_FLUSH_CACHE)James Hilliard
Add the target sysmips dispatcher and implement MIPS_FLUSH_CACHE as a successful no-op for linux-user. Self-modifying code is handled by QEMU's normal user-mode translation invalidation machinery, so the target ABI only needs the syscall command to be accepted. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-2-philmd@linaro.org>
2026-04-25linux-user: Define SO_TIMESTAMP*_NEW and SO_RCVTIMEIO_NEWHelge Deller
Define the entries which always use the 64-bit timestamps. Signed-off-by: Helge Deller <deller@gmx.de>
2026-04-25linux-user/mips: sync k0 TLS for EF_MIPS_MACH_OCTEON userlandsJames Hilliard
Cavium Octeon userspace is not following a generic MIPS Linux TLS ABI rule here. Older Octeon glibc uses the k0 register as the fast thread pointer, while newer Octeon2 and Octeon3 glibc variants use the normal rdhwr $29 path. linux-user already updates CP0_UserLocal for cpu_set_tls() and TARGET_NR_set_thread_area, but it does not keep gpr[26] synchronized. That leaves EF_MIPS_MACH_OCTEON userlands able to complete set_thread_area() and still reach pthread startup or pthread_self() with a stale k0 value. Use the existing MIPS ELF machine flags from linux-user/elfload.c and mirror CP0_UserLocal into gpr[26] only for EF_MIPS_MACH_OCTEON. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Helge Deller <deller@gmx.de>
2026-03-05linux-user: make syscall emulation interruptibleFlorian Hofhammer
The syscall emulation code previously wasn't interruptible via cpu_loop_exit(), as this construct relies on a longjmp target that is not live anymore in the syscall handling code. Consequently, longjmp() would operate on a (potentially overwritten) stale jump buffer. This patch adds an additional setjmp and the necessary handling around it to make longjmp() (and by proxy cpu_loop_exit() safe to call even within a syscall context. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Florian Hofhammer <florian.hofhammer@epfl.ch> Link: https://lore.kernel.org/qemu-devel/20260305-setpc-v5-v7-3-4c3adba52403@epfl.ch Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-01-23linux-user: Add missing termios baud ratesVivian Wang
Add several missing baud rates and inputs baud rates in cflag_tbl. Add these missing definitions in termbits.h: - TARGET_BOTHER for alpha, hppa, ppc, sh4, sparc - TARGET_IBSHIFT for hppa, mips, ppc, sh4, sparc - Missing standard baud rates for hppa These are required for the glibc test tst-termios-linux. Link: https://lore.kernel.org/qemu-devel/20251203-linux-user-higher-baud-rates-v2-1-e45b35224437@iscas.ac.cn Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Helge Deller <deller@gmx.de>
2026-01-23linux-user: Add termios2 support to mips targetLuca Bonissi
Signed-off-by: Luca Bonissi <qemu@bonslack.org> Link: https://lore.kernel.org/qemu-devel/361aa9c5-4464-4d27-8a2c-9ab767324530@bonslack.org Reviewed-by: Helge Deller <deller@gmx.de>
2025-09-17bsd-user, linux-user: introduce qemu_process_cpu_eventsPaolo Bonzini
Add a user-mode emulation version of the function. More will be added later, for now it is just process_queued_cpu_work. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-09-02linux-user/mips: Select M14Kc CPU to run microMIPS binariesPhilippe Mathieu-Daudé
The M14Kc is our latest CPU supporting the microMIPS ASE. Note, currently QEMU doesn't have 64-bit CPU supporting microMIPS ASE. Cc: qemu-stable@nongnu.org Fixes: 3c824109da0 ("target-mips: microMIPS ASE support") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3054 Reported-by: Justin Applegate <justink.applegate@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250814070650.78657-4-philmd@linaro.org>
2025-09-02linux-user/mips: Select 74Kf CPU to run MIPS16e binariesPhilippe Mathieu-Daudé
The 74Kf is our latest CPU supporting MIPS16e ASE. Note, currently QEMU doesn't have 64-bit CPU supporting MIPS16e ASE. Cc: qemu-stable@nongnu.org Fixes: 6ea219d0196..d19954f46df ("target-mips: MIPS16 support") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3054 Reported-by: Justin Applegate <justink.applegate@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250814070650.78657-3-philmd@linaro.org>
2025-08-30linux-user: Standardize on ELF_MACHINE not ELF_ARCHRichard Henderson
PowerPC was the one outlier that defined both ELF_ARCH and ELF_MACHINE; ELF_ARCH was defined incorrectly, necessitating the definition of elf_check_arch. However, the elf file header field in question is called e_machine, so ELF_MACHINE is in fact the better name. Mechanically change most target/target_elf.h files, then adjust ppc/target_elf.h manually. Do not provide a default for ELF_MACHINE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf parameters to {mips,mips64}/target_elf.hRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/mips: Use target_ulong for target_elf_greg_tRichard Henderson
Make use of the fact that target_elf_gregset_t is a proper structure. The target_ulong type matches the abi_ulong/abi_ullong selection within mips64/target_elf.h. Drop ELF_NREG, target_elf_greg_t, and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/mips: Create target_ptrace.hRichard Henderson
Move the target_pt_regs structure from target_syscall.h. Fix the incorrect ordering of the fields. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to mips/elfload.cRichard Henderson
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-28linux-user/mips: Create init_main_threadRichard Henderson
Merge init_thread and target_cpu_copy_regs. There's no point going through a target_pt_regs intermediate. Note that init_thread had set cp0_status in target_pt_regs, but target_cpu_copy_regs did not copy to env. This turns out to be ok because mips_cpu_reset_hold initializes CP0_Status properly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-28linux-user: Move get_elf_base_platform to mips/elfload.cRichard Henderson
Pass in CPUState; define HAVE_ELF_BASE_PLATFORM. Since this was the only instance of ELF_BASE_PLATFORM, go ahead and provide the stub definition for other platforms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-28linux-user: Move get_elf_hwcap to mips/elfload.cRichard Henderson
Change the return type to abi_ulong, and pass in the cpu. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-28linux-user: Move get_elf_cpu_model to target/elfload.cRichard Henderson
Rename from cpu_get_model to emphasize that this is an elf-specific function. Declare the function once in loader.h. This frees up target_elf.h for other uses. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-28linux-user: Create target/elfload.c filesRichard Henderson
Prepare to split the main linux-user/elfload.c. Create empty files for each target, and add the common build rule. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-07-10linux-user/mips/o32: Drop sa_restorer functionalityThomas Weißschuh
The Linux kernel dropped support for sa_restorer on O32 MIPS in the release 2.5.48 because it was unused. See the comment in arch/mips/include/uapi/asm/signal.h. Applications using the kernels UAPI headers will not reserve enough space for qemu-user to copy the sigaction.sa_restorer field to. Unrelated data may be overwritten. Align qemu-user with the kernel by also dropping sa_restorer support. Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250709-mips-sa-restorer-v1-1-fc17120e4afe@t-8ch.de>
2024-12-20user: Move 'linux-user/cpu_loop-common.h' -> 'user/cpu_loop.h'Philippe Mathieu-Daudé
"linux-user/cpu_loop-common.h" is generic enough to be used by bsd-user, so rename it as "user/cpu_loop.h". Mechanical change running: $ sed -i -e 's,cpu_loop-common.h,user/cpu_loop.h,' \ $(git grep -l cpu_loop-common.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-17-philmd@linaro.org>
2024-12-20user: Forward declare target_cpu_copy_regs structurePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-16-philmd@linaro.org>
2024-09-27Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
target/ppc: Fix lxvx/stxvx facility check linux-user: update syscall_nr.h to Linux v6.10 linux-user: update syscall.tbl to Linux v6.11 tcg: Fix iteration step in 32-bit gvec operation tcg: Propagate new TCGOp to add_as_label_use tcg/*: Do not expand cmp_vec, cmpsel_vec early tcg/optimize: Fold movcond with true and false values identical tcg/optimize: Optimize cmp_vec and cmpsel_vec tcg/optimize: Optimize bitsel_vec tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments # -----BEGIN PGP SIGNATURE----- # # iQFQBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmbwBsIdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/bzwf40V8fsRhfc8u/k2Xw # +bXyfyX7ydgB+82YoO71+Wy15ntmYmbL/6O9kGuJXWX8HRDrAR8Js9zDgveysw5m # m/EG+XAbVjYhjaoaaz2nfr+5auQoos9NoCji3s3UJln6sCuZ2Enl0DTFluoHZfgr # /YVAghJ4dwH0hfzO9kmsKmJ9I19HugMMN4dNvEcjQyDDUhgGGjkUaRtGNxwuiwuf # ArL2XhFauXgloryDmpUKQ0BJJ0t8rdPlaRJ8dHqJUnJwav0TW3QVXbrs8gOkmmbg # 9plYTC9DlTguQobvapCDVjiGy/6yuSF/AUpcdQbTRtTi3BrzhTydfLlOtI64GtaQ # OBKd # =ID/g # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Sep 2024 13:00:02 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits) linux-user: update syscall.tbl to Linux v6.11 linux-user,loongarch: move to syscalltbl file linux-user,hexagon: move to syscalltbl file linux-user,riscv: move to syscalltbl file linux-user,openrisc: move to syscalltbl file linux-user,aarch64: move to syscalltbl file linux-user: update syscall.tbl to Linux v6.10 linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10 linux-user: update syscall_nr.h to Linux v6.10 target/ppc: Fix lxvx/stxvx facility check tcg/s390x: Optimize cmpsel with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec tcg/ppc: Optimize cmpsel with constant 0/-1 arguments tcg/ppc: Implement cmpsel_vec tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Add predicate parameters to tcg_out_evex_opc tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/optimize: Optimize bitsel_vec ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-22linux-user: update syscall.tbl to Linux v6.10Laurent Vivier
Updated running scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240918074256.720617-4-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10Laurent Vivier
Updated running scripts/update-mips-syscall-args.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240918074256.720617-3-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-20license: Update deprecated SPDX tag GPL-2.0 to GPL-2.0-onlyPhilippe Mathieu-Daudé
The 'GPL-2.0' license identifier has been deprecated since license list version 3.0 [1] and replaced by the 'GPL-2.0-only' tag [2]. [1] https://spdx.org/licenses/GPL-2.0.html [2] https://spdx.org/licenses/GPL-2.0-only.html Mechanical patch running: $ sed -i -e s/GPL-2.0/GPL-2.0-only/ \ $(git grep -l 'SPDX-License-Identifier: GPL-2.0[ $]' \ | egrep -v '^linux-headers|^include/standard-headers') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-08-20linux-user/mips: Do not try to use removed R5900 CPUPhilippe Mathieu-Daudé
R5900 emulation was removed in commit 823f2897bd. Remove it from ELF parsing in order to avoid: $ qemu-mipsn32 ./test5900 qemu-mipsn32: unable to find CPU model 'R5900' This reverts commit 4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537. Fixes: 823f2897bd ("target/mips: Disable R5900 support") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240814133928.6746-2-philmd@linaro.org>
2024-03-13linux-user: Move tswap_siginfo out of target codeGustavo Romero
Move tswap_siginfo from target code to handle_pending_signal. This will allow some cleanups and having the siginfo ready to be used in gdbstub. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240309030901.1726211-3-gustavo.romero@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Introduce get_task_state()Ilya Leoshkevich
A CPU's TaskState is stored in the CPUState's void *opaque field, accessing which is somewhat awkward due to having to use a cast. Introduce a wrapper and use it everywhere. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240219141628.246823-3-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-4-alex.bennee@linaro.org>
2023-10-18linux-user/mips: fix abort on integer overflowMikulas Patocka
QEMU mips userspace emulation crashes with "qemu: unhandled CPU exception 0x15 - aborting" when one of the integer arithmetic instructions detects an overflow. This patch fixes it so that it delivers SIGFPE with FPE_INTOVF instead. Cc: qemu-stable@nongnu.org Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Message-Id: <3ef979a8-3ee1-eb2d-71f7-d788ff88dd11@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-01linux-user: Split out cpu/target_proc.hRichard Henderson
Move the various open_cpuinfo functions into new files. Move the m68k open_hardware function as well. All other guest architectures get a boilerplate empty file. Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-08linux-user: Define ELF_ET_DYN_BASE in $guest/target_mman.hRichard Henderson
Copy each guest kernel's default value, then bound it against reserved_va or the host address space. Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-08linux-user: Define TASK_UNMAPPED_BASE in $guest/target_mman.hRichard Henderson
Provide default values that are as close as possible to the values used by the guest's kernel. Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-15linux-user: Split TARGET_PROT_* out of syscall_defs.hRichard Henderson
Move the values into the per-target target_mman.h headers Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230707204054.8792-8-richard.henderson@linaro.org>
2023-07-15linux-user: Split TARGET_MAP_* out of syscall_defs.hRichard Henderson
Move the values into the per-target target_mman.h headers Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230707204054.8792-7-richard.henderson@linaro.org>
2023-05-17linux-user: Fix mips fp64 executables loadingDaniil Kovalev
If a program requires fr1, we should set the FR bit of CP0 control status register and add F64 hardware flag. The corresponding `else if` branch statement is copied from the linux kernel sources (see `arch_check_elf` function in linux/arch/mips/kernel/elf.c). Signed-off-by: Daniil Kovalev <dkovalev@compiler-toolchain-for.me> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230404052153.16617-1-dkovalev@compiler-toolchain-for.me> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-30linux-user/mips: Use P5600 as default CPU to run NaN2008 ELF binariesPhilippe Mathieu-Daudé
Per the release 6.06 revision history: 5.03 August 21, 2013 • ABS2008 and NAN2008 fields of Table 5.7 “FCSR RegisterField Descriptions” were optional in release 3 and could be R/W, but as of release 5 are required, read-only, and preset by hardware. The P5600 core implements the release 5, and has the ABS2008 and NAN2008 bits set in CP1_fcr31. Therefore it is able to run ELF binaries compiled with EF_MIPS_NAN2008, such the CIP United Debian NaN2008 distribution: http://repo.oss.cipunited.com/mipsel-nan2008/README.txt In order to run such compiled binaries, select by default the P5600 core when the ELF 'MIPS_NAN2008' flag is set. Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230327162444.388-1-philmd@linaro.org>
2022-09-27linux-user: Provide MADV_* definitionsIlya Leoshkevich
Provide MADV_* definitions using target_mman.h header, similar to what kernel does. Most architectures use the same values, with the exception of alpha and hppa. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220906000839.1672934-2-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-01linux-user: Move generic TARGET_RLIMIT* definitions to generic/target_resource.hSerge Belyshev
Signed-off-by: Serge Belyshev <belyshev@depni.sinp.msu.ru> Message-Id: <87ee4ql3yk.fsf_-_@depni.sinp.msu.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11target/mips: Extract trap code into env->error_codeRichard Henderson
Simplify cpu_loop by doing all of the decode in translate. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11target/mips: Extract break code into env->error_codeRichard Henderson
Simplify cpu_loop by doing all of the decode in translate. This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11linux-user/mips: Use force_sig_faultRichard Henderson
Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP and SIGFPE; use force_sig (SI_KERNEL) for EXCP_DSPDIS. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-16-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11linux-user/mips: Improve do_breakRichard Henderson
Rename to do_tr_or_bp, as per the kernel function. Add a 'trap' argument, akin to the kernel's si_code, but clearer. The return value is always 0, so change the return value to void. Use force_sig and force_sig_fault. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-08 10:39:28 +0000