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* changes:
docs(nbxv3): fix DDR FIP build instructions
feat(nbxv3): print the RCW build stamp from BL2
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* changes:
docs(maintainers): remove "Orphan" maintainer
docs(maintainers): remove build definitions for CMake entry
docs(maintainers): add people to CC along with code owners
docs(maintainers): remove github links
docs(maintainers): reflect code owners with Gerrit's configuration
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* changes:
docs(versal): add build variant macro for Versal Premium Gen 2
feat(versal): add TL support in versal premium gen 2
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integration
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If any bit of code is orphaned then it simply doesn't have a maintainer.
We do not have a status field to encode this rationally and listing a
code owner is only confusing.
Change-Id: I9efdb7757ec1248fd128464726028ce45c78ef58
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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It's a catch-all rule that doesn't carry any meaning. Remove it so that
more specific rules can take precedence.
Change-Id: I5714755bd5c68555eb439b91f7e39632eac85022
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Gerrit is configured to CC particular people on file matches. Reflect
this in the code owners section. It is also generally useful if people
want to stay up to date with parts of the repository.
Change-Id: I9a7d615a72154fe38332a3ae7d5714053aad1be0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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For review purposes all we need is the person's name and email address.
People's GitHub accounts are only needed for account tracking purposes
which aren't really visible on gerrit or relevant to the review process.
They also introduce a lot of duplicate information as each maintainer
role requires two lines. So remove them from the maintainers list to
streamline it.
Change-Id: Id0663ee6a597f433c24244abb65daeb147451584
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Over the past few months some code owners have become inactive and
others have not been reflected on the list despite gerrit being
configured to notify them. Update the list to the latest view of
notification and code owner status.
Change-Id: I14c2c53dde02def4cf52017658e545b6f1a35370
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Document the new Versal Premium Gen 2 PLAT_VARIANT. This covers the
requirement to run BL31 from DDR only, and the new Transfer List (TL)
handoff support, which replaces the old device-tree handoff method.
It also covers the build options and the handoff base addresses that
can be overridden.
Change-Id: Idb0aec5b6dafae8d9f6b863b40c3cd5bde739d01
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
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Add a platform hook in the rxtx_map handler code path that allows
platforms to validate the memory regions provided. This requires
platform specific knowledge of allocated memory regions, so is done
through a platform hook.
Also add appropriate documentation to explain the use of this hook to
any platform integrators.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Iddc953c53a89052103561d62db051f1954334fed
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This is a C variant of the Cortex-X1 core. Copy its enablement and port
any errata that also apply - most of the errata on the original are not
present on the C variant.
Change-Id: Idd8eba7e99abd0839eafde53bd69d9b20a88ed1a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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This is an AE variant of the Cortex-A520 core. Copy its enablement and
port any errata that also apply - most of the errata on the original are
not present on the AE variant.
Change-Id: Ic34b7e3b5e4a9defe79c11be0b3251f6275b5303
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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The DDR FIP target was spelled with a hyphen (fip-ddr) instead of
fip_ddr.
Add the Synopsys DDR PHY training firmware prerequisite which
is in fact the same for any lx2160 platform.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Change-Id: I4be18c1c7ba0c88e2863f9c64a4f7a18b48b3232
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The PBI set a version "YYYYMMDD" into the DCFG SCRATCHRW13 in BCD words.
Let's read this register and display it in order to know the RCW version
this BL2 is running with.
Depending on the carriers, the RCW version banners can be:
Iliad nbxv30 RCW v.20260820
Iliad nbxv32 RCW v.20260820
etc.
It is packed into SCRATCHRW13:
31 28 27 24 23 16 15 8 7 0
+-------+-------+-------+-------+-------+
|CARRIER| TAG | YY | MM | DD | all BCD
+-------+-------+-------+-------+-------+
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Change-Id: I07e13ee8655c1d5d318a69248fb7edcd644ea35a
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* changes:
fix(cpus): add workaround for C1-Nano erratum 4497400
fix(cpus): add workaround for Cortex-A520 erratum 4491980
fix(cpus): add workaround for Cortex-A510 erratum 4568615
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The Versal, Versal NET and Versal Gen 2 platform documents still carried
Markdown code fences (```bash ... ```) and single-backtick inline literals
left over from the original Markdown files. These do not render as code
blocks or literals under Sphinx.
Convert the shell snippets to the ".. code:: bash" RST directive, switch
inline markup to double-backtick literals, add the blank lines required
for nested bullet lists, and fix the stray Markdown heading in the Versal
PLM->TF-A parameter passing section.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If67cc2489e3d28e2852340f4272eaa8a9567b507
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Add support for asynchronous IDE key management operations in FIRME.
In the FIRME IDE Key Management ABIs, the platform implementation
defined mechanism used to manage IDE keys may delegate the requested
operation to a Trusted Subsystem. In such cases FIRME completes the
invocation of the IDE key management ABI after delegating the operation.
The patch adds support for the caller to poll the status of the
operation via the FIRME_IDE_KEYSET_POLL ABI until the operation
completes.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I331207ffabcc9b330ee390bb6707d98f9054bddd
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The firmware build-time hardware configuration may differ from the
hardware available at runtime. Add a platform hook to report the
supported FIRME service mask so BL31 can disable unavailable services
during FIRME initialization.
This lets platforms avoid advertising services they cannot support, such
as attestation services when HES is absent. A weak default
implementation preserves the existing behavior by enabling all
compiled-in FIRME services.
Change-Id: Iff3fc4573f1933380ba91caaabcf636cb20fbfec
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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It's easily forgotten so add it to the checklist as a reminder.
Change-Id: I8eeca2b13c6f4cced5f1437881615606a3e0aeb4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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integration
* changes:
fix(docs): don't say FEAT_AMU isn't contexted
docs(cpufeat): add a note about PSTATE bits and new features
feat(docs): add commit message guidelines for new feature additions
refactor(cpufeat): move FEAT_TRBE constraints to constraints.mk
fix(cpufeat): remove FEAT_SEBEP
refactor(cpufeat): always use is_feat_abc_supported()
fix(el3-runtime): add the target EL check for PSTATE.EXLOCK
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The weakness is that EL3's secret data may be exposed to a lower EL via
a side channel. The workaround is to overwrite any data in this side
channel with publicly visible data using a core specific sequence.
SDEN: https://support.arm.com/documentation/SDEN-3273788
Change-Id: I6ca4b63ca187fe17dc317e10ec3b4b42fdab1b8d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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With the introduction of locking the version negotiation when a non
FFA_VERSION ABI is called, we need to update the documentation for
FFA_VERSION in the el3 spmc to reflect this.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I0a7358a3afdfc99587ce7e38becf3c1bfda6ea5d
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integration
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C1-Pro erratum 3773617 affects revision r1p1 and is fixed in
revision r1p2. It causes ICH_VMCR_EL2.VBPR1 to return incorrect data
when it is written with one SCR_EL3.NS value and subsequently read
with the other.
The required SCR_EL3.NS handling when saving and restoring ICH_VMCR_EL2
is already implemented. Register C1-Pro erratum 3773617 with the
existing common workaround so that it is applied on r1p1.
Refer https://support.arm.com/documentation/SDEN-3273080/latest
Change-Id: I9b83add5d104f4621520c8e90777f10c7a97dad5
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>
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The weakness is that EL3's secret data may be exposed to a lower EL via
a side channel. The workaround is to overwrite any data in this side
channel with publicly visible data using a core specific sequence.
SDEN: https://support.arm.com/documentation/SDEN-2444153
Change-Id: I69e7ead39200c627461ae4d54b2b291579605847
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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The weakness is that EL3's secret data may be exposed to a lower EL via
a side channel. The workaround is to overwrite any data in this side
channel with publicly visible data using a core specific sequence.
SDEN: https://support.arm.com/documentation/SDEN-1873351
Change-Id: I00b76de0a51e60b818c271c6341bcf6682e25da6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Update the entry and list R-Car Gen3, Gen4, Gen5 which are all supported.
Update email address to an up to date one. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ife1197632f7854e1034fe5ccae290705f84b4e19
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Platforms can enable optional cpu architectural features using
runtime detection. FVP currently maintains these settings directly
in its platform Makefile, making the configuration difficult to
reuse and keep consistent with other future platforms.
This change moves the settings into make_helpers/all_features.mk
and includes the file from the FVP makefile.
Updates the architectural feature documentation.
Change-Id: Ifcd97824cbbe6df7578ff0d3728cd6f3582c6312
Signed-off-by: Alcaeus Lam <alcaeus.lam@arm.com>
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* changes:
feat(k3low): add am62l3-beaglebadge board support
refactor(k3low): centralize common board configs
feat(k3low): make DDR configuration board-specific
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Occasionally, a new feature will add a PSTATE bit. That needs to be
considered for injection purposes so add a note to remind about that.
Change-Id: I5e1f8fbd16bfe18c1b3a9be3f37ce0d3f3b001b3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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The Arm ARM is an enormous document so sometimes it's difficult to
figure out when a new feature was added and what its enablement means.
Add a line to remind people to include the version, hopefully reminding
reviewers to update their document, and to mention anything that's not
just "set these bits" for future reference.
Change-Id: I1692ddc78670f8839059d06aeaa5287887d84c65
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Version M.b of the Arm ARM lists the feature as withdrawn as it was not
accepted by the community. Remove it from TF-A too.
Change-Id: I81e6f73ec3e96e3f682e0a97b4496c986fbc88f6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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* changes:
feat(arm): support PSCI idle states for platforms with 2 core PDs
feat(dsu): support new L2Core PD PPU states
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Allow board-specific DDR configurations to be selected via the
K3LOW_DDR_CFG_HEADER build variable without modifying the SoC driver.
Each board can now set its own DDR config header in board.mk, making
it easier to support multiple DDR configurations across different
AM62L boards.
- Move DDR header include from hardcoded driver reference to dynamic
macro
- Define K3LOW_DDR_CFG_HEADER in board.mk as board-specific config
- Add build-time validation to ensure K3LOW_DDR_CFG_HEADER is set for
BL1 builds
Change-Id: I7dc436bd06959e3ccd6290d5da43d21cd5fb4a18
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
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* changes:
feat(crypto): support AES-256-CCM decryption in runtime via PSA API
feat(crypto): add support for AES CCM decryption in runtime
feat(encrypt-fw): add support for AES-256-CCM
refactor(encrypt-fw): rename file with the gcm_encrypt() implementation
feat(fvp): increase BL1 max size for when DECRYPTION_SUPPORT is enabled
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This adds on top of previous work for encryption support in the
encrypt_fw tool. It introduces the support for having
`DECRYPTION_SUPPORT=aes_ccm` in the build system and image decryption
in runtime.
Change-Id: Ia93c87265b1d8a2ceceeeafc7780d4032a09b6b8
Signed-off-by: Cesar Pastorini <cesar.pastorini@arm.com>
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FEAT_TRBE_EXC adds support for reporting trace buffer management events
as TRBE profiling exceptions.
This feature can be found in the M.a version of the Arm ARM.
Change-Id: I148dacfb6445e769820dd265a7d64e3b8c6e8ca2
Signed-off-by: Johann Scott <johann.scott@arm.com>
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Some ST files in dt-bindings directories were not properly listed for
ST maintained files. Add a star at the beginning of the files to list
for example: include/dt-bindings/clock/st,stm32mp21-rcc.h
Change-Id: I87e0f7860de6e7cfed7ba330a899c927320d4dd8
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Add a simple initial Nix Flake which builds the firmware binaries for
the default TF-A build configuration (AArch64 FVP).
Nix Flakes are a standardised way to define a project's dependencies,
development environment, and build outputs using the Nix package
manager.
The key idea behind Flakes is reproducibility: anyone using the flake
gets the same versions of tools and dependencies on any machine where
Nix runs.
This Flake is not considered stable, and provides only a single
preliminary output to allow us to evaluate its suitability for building
reproducible TF-A binaries across different build environments.
To get started with building the flake, install Nix and run:
nix build --extra-experimental-features "nix-command flakes"
Change-Id: Ib03288a556ae52b8401894fe45b7a2f8bf21f401
Signed-off-by: Chris Kay <chris.kay@arm.com>
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Add DSU_PDL2_SUPPORT flag to be used for platforms
with both L1 and L2 core power domains.
When enabled, this exposes functions which can be
called in PSCI platform hooks to control the fate of
the L1 and L2 core PPUs.
configure_core_l2pd_power_required writes to the NOL2PWRDN
core register, indicating whether the L2 power domain can
request power down when all its L1PD cores are powered down.
The new configure_core_wfi_ functions write to the WFI
retention control registers. This sets a timer of system
counter ticks before the core dynamically enters a retention
state upon wfi. These functions can be used in PSCI platform
hooks to create PSCI idle states that force core retention.
When the LOGICRET timer elapses in WFI, the core PDL1 enters
the LOGIC_RET PPU mode. PDL2 remains ON.
When the FULLRET timer elapses in WFI, both L1 and L2 PDs for
the core will enter the FULL_RET PPU mode.
Change-Id: Ib210f2673cad195e9e67031a477e6c8946aff765
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
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Change the BDF mapping upper bound from exclusive to inclusive
and update the Boot Manifest data passed to RMM.
Change-Id: I58f2586636f40e934aec16b21eed3a1916c5a108
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
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Populate the security advisory table with the TFV-12 through
TFV-17 titles.
Change-Id: I17705b3a2ca2a04ee5698fb86b0d2524033e37a1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
LTS-candidate: yes
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Update Jens Wiklander's email address to @oss.qualcomm.com.
Signed-off-by: Jens Wiklander <jens.wiklander@oss.qualcomm.com>
Change-Id: If28f173d2ce78baca8a6483b62df53511c88986d
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* changes:
docs(maintainers): add Nodebox v3 (nbxv3) maintainer
docs(nbxv3): add Nodebox v3 platform documentation
feat(nbxv3): add Nodebox v3 (nbxv3) platform port
feat(changelog): add nbxv3 scope
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Architecturally, from a lower EL perspective, there is no difference
between FFH and KFH as the syndrome registers do not have
differentiating fields. As such, a "FFH test" doesn't make sense - the
lower EL can trigger the behaviour and check the outcome, but it cannot
check how TF-A went about achieving that outcome.
Further, not signalling a synchronous EA is also incorrect in the
generic case- an invalid access should not be upgraded to valid without
emulating valid behaviour.
Change-Id: Ic213bdaf61ad19da017073052e1be4db30e18d95
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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integration
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