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AgeCommit message (Expand)Author
3 daystarget/hexagon: decode the DMA insts as unimpBrian Cain
3 dayshexagon: raise imprecise exception for multi-TLB matchesBrian Cain
3 daystarget/hexagon: assert guest register pair alignmentBrian Cain
3 daystarget/hexagon: kick vCPU when re-asserting interruptsBrian Cain
3 daystarget/hexagon: read BADVA as an alias of BADVA0/1Brian Cain
4 daystarget/riscv: prevent abrupt abortion on unassigned value write to tdataAbhigyan Kumar
4 daystarget/riscv: preserve vl on element-zero faultZephyr Li
4 daystarget/riscv/tcg: fix user option hash table leaksTANG Tiancheng
4 daysdisas/riscv.c: Correct dasm for cbo and lqFrédéric Pétrot
4 daystarget/riscv/tcg/debug: set tinfo version if sdtrig enabledDaniel Henrique Barboza
4 daystarget/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0Daniel Henrique Barboza
4 daystarget/riscv/tcg/debug.c: add Debug 1.0 'pending' bitDaniel Henrique Barboza
4 daystarget/riscv: split 'debug' and 'sdtrig' flagsDaniel Henrique Barboza
5 dayshw/riscv: remove machines-qom.hPierrick Bouvier
5 dayshw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfacesPierrick Bouvier
5 dayshw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINEPierrick Bouvier
5 dayshw/arm: remove machines-qom.hPierrick Bouvier
5 dayshw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfacesPierrick Bouvier
5 dayshw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINEPierrick Bouvier
5 daystarget/arm: Return immediately on error in kvm_arch_init()Jean-Philippe Brucker
5 daystarget/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart()Philippe Mathieu-Daudé
5 daystarget/tricore: Document architectural interrupts as not implementedPhilippe Mathieu-Daudé
5 daystarget/sparc: Constify CPUSPARCState for various cpu_*() gettersPhilippe Mathieu-Daudé
5 daystarget/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()Philippe Mathieu-Daudé
5 daystarget/s390x: Constify S390CPU for cpu_has_*() gettersPhilippe Mathieu-Daudé
5 daystarget/mips: Constify CPUMIPSState for various cpu_*() gettersPhilippe Mathieu-Daudé
5 daystarget/loongarch: Constify LoongArchTLBPhilippe Mathieu-Daudé
5 daystarget/i386: Constify CPU*State for cpu_*_interrupt() gettersPhilippe Mathieu-Daudé
5 daystarget/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()Philippe Mathieu-Daudé
5 daystarget/avr: Constify CPUAVRState for some cpu_*() gettersPhilippe Mathieu-Daudé
5 daystarget/i386: Remove const qualifier in ptw_setl*()Philippe Mathieu-Daudé
6 daysMerge tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu into stagingPeter Maydell
6 daysMerge tag 'pull-target-arm-20260901' of https://gitlab.com/pm215/qemu into st...Peter Maydell
6 daystarget/hexagon: invalidate translated code for user icinvaBrian Cain
6 daystarget/hexagon: fix iassign{r, w} to cover all threadsBrian Cain
6 daystarget/hexagon: implement direct-to-guest interrupt deliveryBrian Cain
6 daystarget/hexagon: raise imprecise exception on multi-TLB matchBrian Cain
6 daystarget/hexagon: read UTIMERLO/UTIMERHI from the global timerBrian Cain
6 daystarget/hexagon: gate GPCYCLE guest register reads on SSR:CEBrian Cain
6 daystarget/hexagon: take BQL when reading the system pcycle countBrian Cain
6 daystarget/hexagon: guard writes to unimplemented guest registersBrian Cain
6 daystarget/hexagon: align exceptions for user/sysemuBrian Cain
6 daystarget/hexagon: Add an errno mappingBrian Cain
6 daystarget/hexagon: add COREDUMP semihosting operationMatheus Tavares Bernardino
6 daystarget/hexagon: add main arch-specific semihosting operationsMatheus Tavares Bernardino
6 daystarget/hexagon: add semihosting supportMatheus Tavares Bernardino
6 dayssemihosting: add callback to set errorMatheus Tavares Bernardino
6 daystarget/hexagon: add aux functions for guest mem load/storeMatheus Tavares Bernardino
6 daystarget/hexagon: fix PC advancement for non-COF TB terminatorsMatheus Tavares Bernardino
6 daystarget/hexagon: fix store-conditional on big-endian hostsMatheus Tavares Bernardino