index
:
qemu/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-10.0
stable-10.1
stable-10.2
stable-11.0
stable-11.1
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-10.0
staging-10.1
staging-10.2
staging-11.0
staging-11.1
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
tracing
QEMU main repository
QEMU Owners
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
3 days
target/hexagon: decode the DMA insts as unimp
Brian Cain
3 days
hexagon: raise imprecise exception for multi-TLB matches
Brian Cain
3 days
target/hexagon: assert guest register pair alignment
Brian Cain
3 days
target/hexagon: kick vCPU when re-asserting interrupts
Brian Cain
3 days
target/hexagon: read BADVA as an alias of BADVA0/1
Brian Cain
4 days
target/riscv: prevent abrupt abortion on unassigned value write to tdata
Abhigyan Kumar
4 days
target/riscv: preserve vl on element-zero fault
Zephyr Li
4 days
target/riscv/tcg: fix user option hash table leaks
TANG Tiancheng
4 days
disas/riscv.c: Correct dasm for cbo and lq
Frédéric Pétrot
4 days
target/riscv/tcg/debug: set tinfo version if sdtrig enabled
Daniel Henrique Barboza
4 days
target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
Daniel Henrique Barboza
4 days
target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
Daniel Henrique Barboza
4 days
target/riscv: split 'debug' and 'sdtrig' flags
Daniel Henrique Barboza
5 days
hw/riscv: remove machines-qom.h
Pierrick Bouvier
5 days
hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces
Pierrick Bouvier
5 days
hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
Pierrick Bouvier
5 days
hw/arm: remove machines-qom.h
Pierrick Bouvier
5 days
hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces
Pierrick Bouvier
5 days
hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
Pierrick Bouvier
5 days
target/arm: Return immediately on error in kvm_arch_init()
Jean-Philippe Brucker
5 days
target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart()
Philippe Mathieu-Daudé
5 days
target/tricore: Document architectural interrupts as not implemented
Philippe Mathieu-Daudé
5 days
target/sparc: Constify CPUSPARCState for various cpu_*() getters
Philippe Mathieu-Daudé
5 days
target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()
Philippe Mathieu-Daudé
5 days
target/s390x: Constify S390CPU for cpu_has_*() getters
Philippe Mathieu-Daudé
5 days
target/mips: Constify CPUMIPSState for various cpu_*() getters
Philippe Mathieu-Daudé
5 days
target/loongarch: Constify LoongArchTLB
Philippe Mathieu-Daudé
5 days
target/i386: Constify CPU*State for cpu_*_interrupt() getters
Philippe Mathieu-Daudé
5 days
target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()
Philippe Mathieu-Daudé
5 days
target/avr: Constify CPUAVRState for some cpu_*() getters
Philippe Mathieu-Daudé
5 days
target/i386: Remove const qualifier in ptw_setl*()
Philippe Mathieu-Daudé
6 days
Merge tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu into staging
Peter Maydell
6 days
Merge tag 'pull-target-arm-20260901' of https://gitlab.com/pm215/qemu into st...
Peter Maydell
6 days
target/hexagon: invalidate translated code for user icinva
Brian Cain
6 days
target/hexagon: fix iassign{r, w} to cover all threads
Brian Cain
6 days
target/hexagon: implement direct-to-guest interrupt delivery
Brian Cain
6 days
target/hexagon: raise imprecise exception on multi-TLB match
Brian Cain
6 days
target/hexagon: read UTIMERLO/UTIMERHI from the global timer
Brian Cain
6 days
target/hexagon: gate GPCYCLE guest register reads on SSR:CE
Brian Cain
6 days
target/hexagon: take BQL when reading the system pcycle count
Brian Cain
6 days
target/hexagon: guard writes to unimplemented guest registers
Brian Cain
6 days
target/hexagon: align exceptions for user/sysemu
Brian Cain
6 days
target/hexagon: Add an errno mapping
Brian Cain
6 days
target/hexagon: add COREDUMP semihosting operation
Matheus Tavares Bernardino
6 days
target/hexagon: add main arch-specific semihosting operations
Matheus Tavares Bernardino
6 days
target/hexagon: add semihosting support
Matheus Tavares Bernardino
6 days
semihosting: add callback to set error
Matheus Tavares Bernardino
6 days
target/hexagon: add aux functions for guest mem load/store
Matheus Tavares Bernardino
6 days
target/hexagon: fix PC advancement for non-COF TB terminators
Matheus Tavares Bernardino
6 days
target/hexagon: fix store-conditional on big-endian hosts
Matheus Tavares Bernardino
[next]